1. Field of the Invention
The present invention relates to a memory access control apparatus and an image pickup apparatus. More particularly, the present invention relates to a memory access control apparatus and an image pickup apparatus that are capable of greatly reducing an effect involved in frequency change in a machine which performs high-speed data transfer and in which a memory is mounted.
2. Description of the Related Art
In recent years, Double Data Rate (DDR) methods are widely adopted, in which both rising edges and falling edges of a clock signal can be used in synchronization between the circuits in a computer to double the processing efficiency per unit time, compared with a case where the rising edges or the falling edges of the clock signal are used, for example, in order to increase the speed of data transfer between the central processing unit (CPU) and the main memory. In addition, DDR2 resulting from improvement of the performance of the DDR to achieve power saving is also proposed.
In a system having a DDR synchronous dynamic random access memory (SDRAM), a DDR2 SDRAM, or a Low Power Double Data Rate (LPDDR) SDRAM provided therein, control is generally performed so as to change the clock frequency in accordance with, for example, a necessary amount of memory or the operation mode of the system in order to suppress the power consumption. This is because the operation of the system in response to a high-speed clock can increase the power consumption per unit time.
The internal circuits are operated in synchronization with a clock signal that is externally supplied in a system having a DDR SDRAM, a DDR2 SDRAM, or a LPDDR SDRAM provided therein. However, a skew can occur due to the wiring length of signal lines, which is dependent on the circuit layout on the chip, and the skew can appear as a difference in phase between a reference clock and a data strobe signal DQS. Accordingly, it is necessary to accurately perform phase adjustment when data is read out from the DDR SDRAM operating in response to high-speed clocks. For example, a circuit called a delay locked loop (DLL) may be provided in the system for the phase adjustment. The DLL controls the delay time of an external interface, which can be caused by the wiring load or the like, to adjust the synchronization between the external interface and an internal clock. Alternatively, a delay line (DL) may be used for the phase adjustment.
An apparatus that is used in a system having a DDR SDRAM, a DDR2 SDRAM, or an LPDDR SDRAM provided therein to change the clock frequency and that is capable of selectively using either of the DLL and the DL that are provided depending on, for example, the frequency used in a memory controller is proposed (for example, refer to Japanese Unexamined Patent Application Publication No. 2007-310549).
An apparatus capable of compression of moving images in real time is also proposed (for example, refer to Japanese Unexamined Patent Application Publication No. 2005-94294). In the apparatus, the clock frequency of a controller is used as a normal frequency and a wasteful power consumption in a monitoring state is eliminated to lengthen the life of the battery before an instruction to start capturing of a moving image is issued, and a clock change controller greatly increases the clock frequency and an Moving Picture Experts Group (MPEG) converter increases the speed of access to an SDRAM storing reference data and/or search data in encoding of moving image data after the instruction to start capturing of a moving image is issued in order to enable the compression of moving images in real time.